A large variety of devices such as microelectro-mechanical systems (MEMS), and integrated circuits are fabricated by procedures that involve the sequential formation of patterned and unpatterned layers upon a substrate. The formation of such layers generally involves steps such as material formation, e.g. deposition or oxidation steps; material removal, e.g. material etching steps; and/or material patterning steps, e.g. steps involving lithographic processes. The number of different procedures available for accomplishing the desired device layer processing is quite extensive. Texts such as S. Sze, VLSI Technology, McGraw-Hill, 1988, describe the panoply of processing steps available in integrated circuit manufacture. Additionally, many of these integrated circuit fabrication procedures have been adapted for other devices such as MEMS devices and further procedures specific to such devices have also been developed. (For example, see F. E. H. Tay, (Ed.), Materials and Process Integration for MEMS, Springer, 2002 for a description of fabrication procedures used in MEMS formation.)
Exemplary of fabrication techniques used in current generation integrated circuit formation is the damascene procedure for patterning copper interconnections between device structures such as transistors and capacitors. Thus, as shown in FIG. 1, in one example, transistors, 3, including drains, 8, gates, 7 and sources, 5, are produced on substrate, 6, using conventional techniques. Subsequently in the fabrication sequence, a layer such as an insulating layer, 2, is deposited by techniques such as sputtering or chemical vapor deposition. A pattern of trenches, 15, are formed in the insulating layer using conventional photolithographic and dry etching e.g. reactive ion etching, procedures. In one approach, a thin barrier layer such as a tantalum or tantalum nitride layer is deposited in the trench with subsequent formation of a copper seed layer, in turn, on the tantalum or tantalum nitride region. (The seed layer promotes subsequent electrochemical deposition.) Bulk copper is then electrochemically deposited into the trench, 15, and onto the surface of insulating layer, 2. The copper portion lying above trench 15 and on the surface of insulator 2 is removed by chemical-mechanical polishing (CMP) leaving trench 15 filled with copper. Thus the copper interconnects 16 are formed in the pattern of the trenches. Subsequent processing includes for example deposition of layer 17 with patterning and damascene processing of via 12 followed by deposition of an overlying cap layer 14 such as a silicon dioxide, silicon carbide, or silicon nitride layer.
The manufacture in this manner of devices by sequential layer formation leads, in integrated circuits, to a monolithic structure such as shown in FIG. 1. In contrast, MEMS devices are not necessarily monolithic but often include voids or other open areas. For example, MEMS devices designed for chromatographic analysis of very small samples include elongated, straw-like channels that act as chromatography columns. (See for example, D. Banks, Microengineering MEMS and Interfacing: A Practical Guide, CRC Press, 2006 for a description of one such device.) Alternatively, many MEMS structures designed to operate as miniature mechanical machines often require, during formation, the freeing of structures such as gears from the substrate in which such gears are formed. Again, to free the mechanical structure void formation is required. Such result has required techniques not standard to integrated circuit processing. For example, the channels of a microminiature chromatographic column are formed by crystallographically selective etching—a not particularly economic procedure to integrate with standard integrated circuit processing.
It is generally preferable in device formation to use conventional integrated circuit processing techniques. The development of new techniques is frequently a costly task. Additionally, often the use of such techniques requires modification of the processing sequence conventionally used and such techniques possibly are not compatible with the device structures and materials. Thus both this development and the resulting required modifications lead to undesirable cost consequences. Indeed, it is the goal in device processing to eliminate rather than add processing steps while producing economic, conventional or newly emerging devices.